The present invention relates to a semiconductor memory device having plate lines and precharge circuits.
As illustrated in FIG. 1, a semiconductor memory such as a DRAM (dynamic RAM) includes one MOS transistor Q for data transfer and one capacitor C for data storage. The drain of the MOS transistor is connected to a bit line BL, the source thereof is connected to one electrode of the capacitor, and the gate thereof is connected to a word line WL. A connecting point of the source of the MOS transistor Q and the one electrode of the capacitor C serves as a storage node N. The other electrode opposed to the one electrode with a capacitor insulation film interposed therebetween, serves as a plate electrode PL common to a plurality of capacitors C. A potential of, e.g., Vcc/2 is applied from a plate potential generator 10 to the plate electrode PL. The above DRAM is described in Kirihata et al., xe2x80x9cFlexible Test Mode Approach for 256-Mb DRAMxe2x80x9d, IEEE Journal of SOLID-STATE Circuits, Vol. 32, No. 10, October, 1997, pp. 1525-1534.
In a selected memory cell of the foregoing DRAM, the MOS transistor Q is turned on to charge/discharge the capacitor C in the sense/write mode. The potential variations of the storage node N vary the potential of the plate electrode PL and, in other words, noise remains on the plate electrode PL. More specifically, when data xe2x80x9c0xe2x80x9d is written to a memory cell in which data xe2x80x9c1xe2x80x9d (=Vcc) has been stored, the plate potential is varied as shown in FIG. 2. In the case of FIG. 2, the potential amplitude of the bit line BL is changed between Vcc (e.g., 3.3V) and Vss (e.g., 0V), the precharge potential and plate potential of the bit line BL are each set at Vcc/2, and the word line WL is driven at boost potential Vpp (e.g., 4.5V). When the potential of the word line WL rises and the MOS transistor Q turns on, the capacitor C is set in a discharge mode, and the storage node N is decreased in potential, while the bit line BL is charged by the capacitor C and thus increased in potential. In this case, the potential of the plate electrode PL is slightly lowered by capacitance coupling between the plate electrode PL and the electrode alongside the storage node N of the capacitor C. When a sense amplifier starts to operate, the potential variations of the bit line BL are amplified and thus the potentials of both the bit line BL and storage node N are increased to Vcc. As the potential of the storage node N increases, the plate potential slightly increases. When a write operation starts, write data xe2x80x9c0xe2x80x9d is transferred to the bit line BL, and the potentials of the bit line BL and storage node N are each dropped to a Vss level. In response to the variations in potential, the plate potential slightly lowers and then gradually returns to a Vcc/2 level.
As described above, the plate potential varies with an access operation of the memory cells. The variation xcex94VPL of the plate potential is expressed by the following equation (1) using the potential variation AVSN of the storage node N:
xcex94VPL=xcex94VSNxc3x97(Cs/CPL)xe2x80x83xe2x80x83(1)
where Cs is capacitance of the capacitor C and CPL is capacitance of the plate electrode PL (the sum of capacitance of capacitors C sharing one plate electrode PL).
Since the capacitance Cs of the capacitor C is smaller than that CPL of the plate electrode PL, an influence of potential variations of one storage node N upon the plate potential is small. If, however, the potentials of plural storage nodes N are varied in the same direction at the same time, the variation xcex94VPL of the plate potential cannot be ignored. In FIG. 2, the plate potential is almost recovered by one cycle of a selected word line (row cycle: a period during which the word line rises from Vss to Vpp, decreases to Vss and then start to rise next); however, there is a case where the plate potential cannot be recovered within the row cycle because of the resistance of the plate electrode itself, the resistance of wiring between the plate potential generator 10 and plate electrode PL, and the current driving performance of the generator 10. In particular, as the DRAM increases in degree of integration, the electrodes of capacitors C sharing one plate electrode PL increases in number and the capacitance of the plate electrode PL becomes large. Furthermore, the wiring is thinned and lengthened and its resistance between the plate potential generator 10 and the plate electrode PL is heightened. In the row cycle, therefore, the plate potential is more and more difficult to recover.
If a memory cell includes a capacitor C having a large leak, the storage node N and plate electrode PL are short-circuited. Usually such a memory cell is treated as a defective and replaced with a spare memory cell by a redundancy circuit. This defective memory cell is not used for data storage. Since, however, the defective memory cell is not separated from the bit line, the potential variations of the bit line are directly applied to the plate electrode in the sense/write mode, thereby causing great variations in plate potential.
An influence of the above plate potential variations will now be described in detail. Under the circumstance where the plate potential is not varied, the readout voltage Vsense of the bit line BL is expressed by the following equation (2):
Vsense=(Vcellxe2x88x92VBL)xc3x97{Cs/(Cb+Cs)}xe2x80x83xe2x80x83(2)
where Vcell is potential of the storage node N immediately before the potential of the word line WL rises, VBL is precharge potential of the bit line BL, Cs is capacitance of the capacitor C, and Cb is capacitance of the bit line BL.
If the plate potential varies only by xcex94VPL, then the readout voltage Vsense of the bit line BL is given by the following equation (3):
Vsense=(Vcell+xcex94VPLxe2x88x92VBL)xc3x97{Cs/(Cb+Cs)}xe2x80x83xe2x80x83(3)
If the plate potential varies to lower (xcex94VPL less than 0), the readout potential of data xe2x80x9c0xe2x80x9d (Vcell=Vss) decreases and the readout voltage (potential difference) increases in the sense mode. Since, however, the readout potential of data xe2x80x9c1xe2x80x9d also decreases, a margin for reading data xe2x80x9c1xe2x80x9d is reduced. If, by contraries, the plate potential varies to rise (xcex94VPL greater than 0), a margin for reading data xe2x80x9c0xe2x80x9d is reduced in the sense mode.
If the word lines are selected in sequence for high-speed row access, the sense amplifier is operated frequently; therefore, an amount of noise superimposed upon the plate electrode PL is increased and a malfunction will easily be caused due to a reduction in margin. This is one factor which prevents the DRAM from operating at high speed.
An object of the present invention is to provide a semiconductor memory device capable of suppressing potential variations of a plate electrode.
Another object thereof is to provide a semiconductor memory device capable of high-speed access without reducing a margin for readout operations even by potential variations of a plate electrode.
To attain the above objects, according to a first aspect of the present invention, there is provided a semiconductor memory device comprising bit lines, word lines crossing the bit lines, memory cells arranged at intersections of the bit lines and word lines, and including a plurality of capacitors to which a plate electrode is connected in common, an insulation film formed on the plate electrode, a bit-line precharge circuit for precharging the bit lines, and a wiring layer formed on the insulation film and electrically connected to the plate electrode and a power supply terminal of the bit-line precharge circuit.
In the semiconductor memory device so constituted, if the plate electrode common to the capacitors of memory cells is used as power supplies of the bit-line precharge circuits, the potential variations of the plate electrode are suppressed. When the plate potential varies, the precharge potential of the bit lines varies accordingly and these variations are canceled each other at a readout voltage of the memory cells. Consequently a margin for readout operations is not reduced and high-speed access can be achieved. Since the potential stability of the plate electrode is not needed, a low-performance plate potential generator can be used. Since, moreover, the layout of the plate potential generator or the wiring resistance between the plate potential generator and the plate electrode need not be taken into consideration, the degree of freedom of the layout is increased.
Though the plate electrode is low in current supply capability, it can be used as a power supply to correct a difference in bit-line precharge potential sufficiently.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising bit lines, word lines crossing the bit lines, memory cells arranged at intersections of the bit lines and the word lines, the memory cells including a plurality of capacitors to which a plate electrode is connected in common, a first insulation film formed on the plate electrode, a bit-line precharge circuit for precharging the bit lines, a first wiring layer formed on the first insulation film along a direction crossing the bit lines, the first wiring layer being connected to the plate electrode through a first via hole located on the plate electrode of the first insulation film, a second wiring layer formed on the first insulation film along a direction crossing the bit lines, the second wiring layer being connected to a power supply terminal of the bit-line precharge circuit through a contact hole located on the bit-line precharge circuit of the first insulation film, a second insulation film formed on the first wiring layer, the second wiring layer, and the first insulation film, and a third wiring layer formed on the second insulation film along a direction which is equal to that of the bit lines, the third wiring layer being connected to the first wiring layer through a second via hole formed in the second insulation film and the second wiring layer through a third via hole formed in the second insulation film.
In the semiconductor memory device so constituted, a power supply potential is applied from the plate electrode to the bit-line precharge circuits. Therefore, when the plate potential varies, the precharge potential of the bit lines varies accordingly and these variations are canceled each other at a readout voltage of the memory cells. Consequently a margin for readout operations is not reduced and high-speed access can be achieved. Since, furthermore, the plate electrode is connected to the power supply terminals of the bit-line precharge circuits, the power supply wiring thereof need not be routed and thus a chip area can effectively be utilized. Since, moreover, the potential of the plate electrode need not be stabilized, a high-performance plate potential generator is not required, and the layout of the plate potential generator or the wiring resistance between the plate potential generator and plate electrode need not be taken into consideration, thereby improving the degree of freedom of the layout. Moreover, the plate electrode does not pass on the sense amplifier. Even in the shared sense amplifier, noise generated during the operation of the sense amplifier can be inhibited from being added to the plate electrode and a readout margin can be prevented from lowering.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.